Yogesh Jaiswal
Current
Design engineer
Education
B.E. Electronics &comm.
Industry
Semiconductors/Electronics
About Yogesh Jaiswal
I am working as a design Engineer in the Analog and mixed signal Group at Spontey, India. In this role, my primary responsibilities consist of complete layout ownership of several custom analog blocks,building digital macros,Circuit design for standard cell libraries,sizing analysis/study based on model performance and mentoring of young engineers on mixed signal layouts.I began my career as a freelancer with Erockit,India.I re-engineered and characterize the circuits of BMS module
Yogesh Jaiswal ’s experience
Design engineer
at
Spontey Inc
, Gurgaon, INDIA
April 2007 – Currently Working
Industry: Semiconductors/Electronics
Circuit design :-
- Standard cell library circuit design and
characterization Layout design :- - Standard Cell Library (High
Speed and high Density) layout design - SRAM (1-port and 2-port)
layout design - IO Pad Library layout design - IO ring
integration and supply distribution for whole chip - Voltage
Regulator layout design - PLL layout design - LVDS transmitter
and receiver layout design - CML Buffer,CTLE and Bandgap
reference analog layouts design for SERDES chip
characterization Layout design :- - Standard Cell Library (High
Speed and high Density) layout design - SRAM (1-port and 2-port)
layout design - IO Pad Library layout design - IO ring
integration and supply distribution for whole chip - Voltage
Regulator layout design - PLL layout design - LVDS transmitter
and receiver layout design - CML Buffer,CTLE and Bandgap
reference analog layouts design for SERDES chip
Freelancer at Erockit Gmbh , Delhi, INDIA
January 2007 – April 2007
Design and characterization of Battery Management circuit .
Yogesh Jaiswal ’s education
B.E. [Electronics &comm.],
Jaipur Engineering college [October,2005]
, Jaipur, INDIA
PG Diploma [Micro-electronics],
Semiconductor Complex Ltd. Mohali (Department of ISRO) [December,2006] , Chandigarh, INDIA
Yogesh Jaiswal ’s additional information
Interests:
VLSI backend design,Circuit design,Finance,New technology,
Websites:
Awards and achievements:
I was a valedictorian at my University scoring an aggregate of 78% marks.I won several awards like "BEST Student " for all-round performance, Gold medal for topping the college in the final year,I was recognized as the "Most Significant Impact" employee for my work and many more.
News feed
From Yogesh Jaiswal ’s contacts
Immdiate requirements in FE-Verification-2-3 yrs of exp sufficient and
also in full custom layout (MSG layout) and Physical Design-floor
planning,timing closure,Power Ana......more >>
also in full custom layout (MSG layout) and Physical Design-floor
planning,timing closure,Power Ana......more >>
Urgetn requirements in Circuit Design/Physical Design/DFT/Digital
Custom layout Design/PLL/DLL/IO Design/Memory Design and FE-Design and
Verification...more >>
Custom layout Design/PLL/DLL/IO Design/Memory Design and FE-Design and
Verification...more >>
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