Arpit Singhal
Current
Project Trainee
Education
Advance... VLSI Design
Arpit Singhal ’s experience
Project Trainee
at
Ni logics Pvt. Ltd.
, Pune
Currently Working
6 months of experience on Simulation & Synthesis, Formal
Verification, Static Timing Analysis,VHDL&Verilog based RTL
design(ASIC ,FPGA-Front End Design)
Verification, Static Timing Analysis,VHDL&Verilog based RTL
design(ASIC ,FPGA-Front End Design)
Arpit Singhal ’s education
Advance Post Graduate Diploma [VLSI Design],
VEDANT, Semiconductor Complex Limited [December, 2006]
, Mohali
B.Tech [Electronics/Telecommunication],
College of Engineering Roorkee [May, 2006] , Roorkee
AISSCE [Science],
VVABN [May, 2002] , Roorkee
AISSE,
VVABN [May, 2000] , Roorkee
Arpit Singhal ’s additional information
Interests:
VLSI Design
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