As technologies advance, the semiconductor industry faces complexities that demand an ever-increasing operational agility. Driven by the sheer complexity of System-On-Chip (SoC) designs, design verification, the critical quality check to ensure that an integrated circuit works as planned is taking more time in a typical SoC design project. Real Intent, based out of Sunnyvale, CA has been working with semiconductor companies to help them to find faults early on in the design cycle to eliminate failure modes of SoCs.
"Complexities of designing SoCs have gone a notch higher alongside the fact that 40-50 percent of gates used in devices are reusable making the design more complex and difficult in ensuring the functionality is correct," elaborates Prakash Narain, CEO & President, Real Intent. Compounding this scenario, design teams are not located atone nerve center; but rather spread across the globe. To get design activities to flow seamlessly despite the geographical diversity is a challenging task. In this scenario, Real Intent steps in to accelerate early functional verification and advanced sign-off of digital designs. According to Narain, the cost of designing a product depends overtly on the time taken for design and the speed of automation tools that are used. For semiconductor companies it becomes imperative to find the errors and bugs early and ensure that the time required from the design stage to deployment is minimal.
Among the products that Real Intent has in its vast repertoire of solutions that are developed to help semiconductor companies, Ascent Lint is in spotlight for early functional verification and includes smart rules that perform syntax and semantic checks for today's complex SoC designs. Ascent is quite in demand for semiconductor companies for its sheer ability to find errors and ease of debugging capabilities delivering high capacity, and comprehensiveness.
Ascent Auto formal works in tandem with Ascent Lint by hunting for bugs in an automated mode, thus saving time and resources. The above two versions of Ascent, work by combining with Ascent X-Verification System. "Ascent X ensures correction of unnecessary X's (X-pessimism)in Net list and drives cost down by avoiding the monotonous, error-prone debug at the Netlist level," states Narain. The early verification models are use din conjunction with advanced sign-off verification tools of Real Intent like Meridian CDC and Meridian Constraints. Meridan CDC performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC or FPGA devices are received reliably. "The unique technology in Meridian CDC quickly finds bugs that cause chip failures and leads to successful design sign off to physical implementation," adds Narain. Along with Meridan CDC, Meridian Constraints manages the timing budgets used throughout the design stage and eliminates any errors and inconsistencies.
With the bevy of products unleashed in the market by Real intent, success stories also abound. One of these, centers on a leading manufacturer of tests and measurement instruments. With our high accuracy and performance indicator tools, we could demonstrate significantly better accurate results. This enabled very fast iterations necessary for the functional closure and an efficient sign-off process.
"While the design complexities are increasing, the time to market window is short; hence the response time becomes all the more critical when a problem is encountered. Our environment and products are organized in a way to deliver able support, and rapid response time to our customers," affirms Narain. With an expert team of engineers focused on innovation coupled with engineering discipline, Real Intent is developing high quality solutions to address the need for sign-off of digital designs.