Memoir Systems is a provider of unique algorithmic embedded multiport memory intellectual property (IP). Headquartered in Sunnyvale, the company has raised a total of $5.1 million from Lighspeed Venture Partners.

The hot trends seen in embedded memory include the need for higher performance, memory partitioning, and port configurability. Performance improvement by multiporting a memory
is a key requirement as memory clock speeds hit the wall. For an instance, networking and storage systems that have grown beyond 480-640Gb/s, multiport memories are the only practical way to
meet performance demands. Similarly, multicore processor platforms need multiport memory to avoid memory bottlenecks and reach full performance potential. In either case, memory
performance is achieved by parallel processing of memory operations, rather than just cranking up memory clock speeds.




Using the same memory in different ways


The trends of memory partitioning and port configurability address the need to allow a single piece of memory to be used in multiple ways. This requirement is being driven by the designers and manufacturers of application-specific processors whose chips need to cater to different markets. Simply put, partitioning gives the ability to craft out portions of the memory to do the same function but remain independent of the other partitions. For example, instead of a 16 Mb lookup table which does two reads every cycle, you can have two tables: 10 Mb, and a 6Mb table, both of which can individually support two reads per cycle. These are statically defined, but configured at boot time. Port configuration, on the other hand, is changing the definition of the ports to allow reusing the memory in a different mode. For instance, a 4Mb memory can be used as a 2R or 1W memory that does lookups in one application or as a 1R and 1W memory that implements counters in another. A single port configurable memory provides the option to be used in either configuration.


Struggling with physical design and timing closure


With the integration of a huge number of IPs on a die, many of which need to be placed near large capacity and high clock frequency memories, physical design and timing closure has become extremely challenging. Additionally, with large amounts of memory, say 500Mbits on a SoC(System on a Chip), memory reliability, and the resulting chip and system downtime that can occur, become more of a challenge. Statistically, there are more bits that could potentially fail and more errors such as soft errors, hard errors, some row or column errors and weak bit errors.




Algorithms make memory smarter and faster


Algorithmic Memory uses physical single-port memory IP cores and combines them with the power of algorithms to create multiport memories that offer significant benefits over custom multiport physical memories. One of the most compelling advantages is that Algorithmic Memory dramatically increases memory performance by increasing the number of memory accesses that can occur in parallel, thus alleviating the traditional processor-embedded memory gap. Memoir’s memory IP cores have been made available as a standard products that increase the performance of single-port memory by 2X and 4X, and up to 10X more memory operations per second (MOPS) on an as need basis.


The future of memory innovation


Instead of today's 2D or planar CMOS transistors, chip makers are exploring more power-efficient three-dimensional structures called FinFETs. New FinFET-based memory circuits will enable reduced leakage power, and are also expected to slightly improve embedded memory performance. However, any dramatic improvements in embedded performance will likely come from a new technology, potentially a new kind of embedded memory.