The consumer electronics is evolving with each passing day. Smartphones, watches, fitness bands, sensors used in IoT and others encompass amazing capabilities. "From the ability to browse high speed internet, checking heart beat rates to turning on the lights in home, this emergence of consumer electronics is causing a fundamental shift in the way the chips which drive these devices are designed," says Sanjiv Kaul, President and CEO, Calypto. He goes on to say, "The race for time to market has resulted in the adoption and growth of higher level design creation methodologies."

In particular, High Level Synthesis (HLS), an automated design process that interprets an algorithmic description that contains desired functionality-such as recording full HD video or the compression of 5G wireless data- and then generate the implementation of a digital circuit has become very popular. At the same time, designers must use aggressive techniques to create faster and lower power circuits to meet the market needs.

Furthermore, growing complexity has meant dramatically rising costs to verify the designs, another driver for customers to adopt HLS. With expertise in the semiconductor industry, Calypto Design Systems offers best-in-class technologies focused on HLS hardware designs, power optimization and functional verifications. "These technologies empower chip designers to create high quality and low power electronic systems for today's most innovative electronic products," extols Kaul.

Calypto's Catapult high level synthesis platform empowers designers to use popular programming languages such as ANSI C++ and SystemC to describe the required functionality in the hardware and free engineers from much of the detail of implementation. "In fact the 60 thousand lines of C++ code incorporate about 300 thousand lines of RTL (register transfer-level) code," he adds. By raising the abstraction level, Catapult significantly reduces the verification time by more than 2x. Catapult allows ASIC (Application- Specific Integrated Circuit), SoC (System on Chip) and FPGA (Field- Programmable Gate Array) designers to fully explore micro-architecture and interface options, resulting in lower power and lower cost devices.

Similarly, PowerPro, the company's low power design technology for chips automates power optimization by identifying the best design tricks to lower power, and finds 'wasted' power the designer may otherwise be unaware. Engineers can also present real-life scenarios to the tool, which will then suggest ways to modify the design to further minimize power. It enables designers to analyze both static and dynamic power usage at micro levels and either automatically or manually create a power optimized RTL design. "PowerPro has proven to reduce power by up to 60 percent," says Kaul. Finally, SLEC, Calypto's design verification technology handles differences in design state, timing and levels of code executions. "SLEC effectively compares HSL hardware design with real system-level models to validate the overall chip design," he adds.

The ability to design, optimize and verify the chips has helped the company gain many customers including NVIDIA, Google, Qualcomm, Renesas, Olympus, Freescale Semiconductor and STMicroelectronics. In one instance, STMicroelectronics's Home Entertainment and Displays Group (HED) that designs the video decoders and display subsystems wanted to fully demonstrate 3D graphic capability on its latest SoC and there was no time for traditional RTL design. STMicroelectronics was able to meet this goal by moving almost all of the new design work to Catapult HLS.

"As the consumer demand in the home electronics market is a relentless master where chip designers get extremely narrow market windows, the defining factor would be their ability to design a competitive product within the given time frame," says Kaul. "Where every profitable, innovative electronics company is looking for this ability, we offer them one," he concludes.