Monday, November 17, 2008
But the EDA software solutions that he created and worked with over his career are, in Goel’s eyes, reaching their limits. They are low on the computational horsepower required for design of today’s ever more complex chips. As a result, up to 60 percent of the design cycle is being spent in the verification phase.
In 1998 a former hardware designer with a networking background, Subbu Ganesan, approached Goel with what Goel saw as a “very non-intuitive” architecture for a hardware acceleration solution that would seek to outperform the pervasive EDA software solutions currently in the market. The company that Ganesan was pitching was Tharas Systems, which Goel invested in and now manages as president and CEO.
The solution the company built from the initial basic idea is essentially a hardware box that, according to Goel, speeds up that portion of the design verification cycle between the initial design work and the final regression testing by factors of 10x to 50x. It is, Goel explains, “very memory intensive with very little logic.” The box consists of boards with a large number of a single custom application-specific integrated circuit (ASIC) on them. The system allows extensive parallel calculations. Goel clocks his $280,000 product, which he launched in August 2000 and has shipped to a few initial customers, as taking about six to ten minutes to verify a million-gate design.
Goel recalls with a smile, “Actually, my first company put the first hardware acceleration company out of business.” Goel admits that in the 1980s, advancements in software were outstripping what could be achieved with a hardware solution. Today, he is convinced that it is again time for a hardware solution to shine in EDA.
Initial investors Andy Bechtolshiem, Raj Parekh, and Alliance Venture Management seem to share the company’s vision, and it has just raised $4.2 million, co-led by Alliance and Bechtolsheim, with participation from Redwood Ventures.
